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EZ801905050MOD
EZ80190 Module
Product Specification
PS019101-1003 PRELIMINARY
ZiLOG Worldwide Headquarters * 532 Race Street * San Jose, CA 95126 Telephone: 408.558.8500 * Fax: 408.558.8300 * www.ZiLOG.com
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(c) 2003 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. ZiLOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZiLOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. Except with the express written approval ZiLOG, use of information, devices, or technology as critical components of life support systems is not authorized. No licenses or other rights are conveyed, implicitly or otherwise, by this document under any intellectual property rights.
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EZ801905050MOD EZ80190 Module Product Specification
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Table of Contents
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v The EZ80190 Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Module Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 EZ80190 Processor Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 I/O Connector (JP2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Peripheral Bus Connector (JP1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Onboard Component Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Logic-Level I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Onboard Battery Backup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Ethernet Media Access Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Ethernet LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Ethernet Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 GPIO Pins for Enabling LAN Activity, Sleep, Interrupt . . . . . . . . . . . . . 13 EMAC Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 EMAC Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Static RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Real-Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Reset Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Serial Interface Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 ESD/EMI Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Document Number Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Change Log . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Schematic Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Customer Feedback Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
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Table of Contents
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List of Figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. EZ80190 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 3 EZ80190 Module Peripheral Bus Connector Pin Configuration--JP1 4 EZ80190 Module I/O Connector Pin Configuration--JP2 . . . . . . . . . 8 Physical Dimensions of the EZ80190 Module . . . . . . . . . . . . . . . . . 17 EZ80190 Module--Top Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 EZ80190 Module--Bottom Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Power Supply Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 EZ80190 Module Schematic Diagram, #1 of 9--CPU . . . . . . . . . . . 23 EZ80190 Module Schematic Diagram, #2 of 9--36-Pin SRAM Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 EZ80190 Module Schematic Diagram, #3 of 9--NOR Flash Device 25 EZ80190 Module Schematic Diagram, #4 of 9--Ethernet Module . 26 EZ80190 Module Schematic Diagram, #5 of 9--Ethernet Module Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 EZ80190 Module Schematic Diagram, #6 of 9--Ethernet Module Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 EZ80190 Module Schematic Diagram, #7 of 9--Headers . . . . . . . . 29 EZ80190 Module Schematic Diagram, #8 of 9--Power Supply . . . 30
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List of Figures
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List of Tables
Table 1. EZ80190 Module Peripheral Bus Connector Pin Identification. . . . . . . . 5 Table 2. EZ80190 Module I/O Connector Pin Identification . . . . . . . . . . . . . . . . . 8 Table 3. Ethernet Connector Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 4. Chip Frequency to Wait State Cycle Time Calculation. . . . . . . . . . . . . 14 Table 5. Real-Time Clock Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 6. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
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List of Tables
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The EZ80190 Module
The EZ80190 Module is a compact, high-performance Ethernet module specially designed for the rapid development and deployment of embedded systems requiring control and Internet/Intranet connectivity. It features the low-cost EZ80190 microprocessor powered by ZiLOG's latest power-efficient, high-speed eZ80(R) CPU. The EZ80190 microprocessor is a high-speed single-cycle instruction-fetch microprocessor, which can operate with a clock speed of 50 MHz. It can operate in Z80compatible addressing mode (64 KB) or full 24-bit addressing mode (16 MB). The rich peripheral set of the EZ80190 makes it suitable for a variety of applications, including industrial control, communication, security, automation, point-ofsale terminals, and embedded networking applications.
Module Features * * * * * * * * * *
EZ80190 microprocessor operating at 50 MHz Ethernet Media Access Controller+ PHY with RJ45 connector 512 KB zero-wait-state onboard SRAM 1 MB onboard NOR Flash ROM (90-100 ns) Real-Time Clock with 32.768 kHz Crystal with battery backup I/O connector provides 32 general-purpose 5 V-tolerant I/O pinouts Onboard peripheral bus connector provides I/O bus for external peripheral connections (IRQ, CS, 24 address, 8 data) Small footprint 78.7 mm x 63.5 mm; height is 24 mm Module operates from external 3.3 V power supply Standard operating temperature range: 0C to +70C
EZ80190 Processor Features * * * *
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Single-cycle instruction fetch, high-performance, pipelined eZ80(R) CPU core Low power features including SLEEP mode and HALT mode Two UARTs with independent baud rate generators Two SPI interfaces with independent clock rate generators
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The EZ80190 Module
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* * * * * * * * * * * *
Two I2C interfaces with independent clock rate generators Fast multiply accumulate unit (MACC) DMA Controller for fast memory-to-memory transfers Glueless external memory and I/O interface featuring 4 chip selects with individual wait state generators Fixed-priority vectored interrupts (both internal and external) and interrupt controller Six 16-bit Counter/Timers with prescalers and direct input/output drive Watch-Dog Timer 32 bits of general-purpose I/O 2-wire ZDI debug interface 100-pin LQFP package 3.3 V 0.3 V supply voltage with 5V tolerant inputs Standard operating temperature range: 0C to +70C
Note: All signals with an overline are active Low. For example, B/W, for which WORD is active Low, and B/W, for which BYTE is active Low.
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EZ80190 Processor Features
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Block Diagram
Figure 1 illustrates a block diagram of the EZ80190 microprocessor.
Power-On Reset
50MHz Oscillator
PD 60-Pin I/O Connector
32-Bit GPIO
PC
GPIO UART SPI I2C GPIO
ZDI ZDI Watch-Dog Timer MACC
PB
PA GPIO
IC
2
DMA Bus Controller 8-Bit Data 24-Bit Address
Gold Cap
RTC
EMAC
32 kHz XTAL
1 MB Flash/ROM
512 KB SRAM
RJ45
LEDs
Figure 1. EZ80190 Functional Block Diagram
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EZ80190 Processor Features
60-Pin Bus Connector
GPIO UART SPI I2C
eZ80 CPU 6 x 16-Bit Timer
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Pin Description
I/O Connector (JP2)
Figure 2 illustrates the pin layout of the 60-pin Peripheral Bus Connector (JP1) of the EZ80190 Module. The eZ80(R) Development Platform, however, features a 50pin connector. The EZ80190 Module is designed to interface pin 60 of its JP1 connector to pin 50 of the eZ80(R) Development Platform's JP1 connector so that pins 1-10 of the EZ80190 Module overlap the edge of the eZ80(R) Development Platform. Table 1 identifies the pins and their functions.
Figure 2. EZ80190 Module Peripheral Bus Connector Pin Configuration--JP1
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Pin Description
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Table 1. EZ80190 Module Peripheral Bus Connector Pin Identification* Pull Up/Down*
Pin # 1 2 3 4 5 6 7
Symbol Reserved Reserved Reserved Reserved TRSTN Reserved F91_WE
Signal Direction Comments
Input
Reset for On-Chip Instrumentation (OCI); not used with the EZ80190 Module.
PU 10 K
Input
A Low enables a Write to on-chip Flash memory. If this pin is unconnected, on-chip Flash memory is write-protected; not used with the EZ80190 Module.
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
Reserved GND VCC A6 A0 A10 A3 GND VCC A8 A7 A13 A9 A15 A14 Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional VSS/Ground (0 V). 3.3 V supply input pin. VSS/Ground (0 V). 3.3 V supply input pin.
Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0-D7 and A0-A23 should be below 10 pF to satisfy timing requirements for the CPU. All unused inputs should be pulled to either VDD or GND, depending on their inactive levels, to reduce power consumption and to reduce noise sensitivity. To prevent EMI, the EZ80CLK output can be deactivated via software in the EZ80190 Peripheral Power-Down Register. All inputs are CMOS level 3.3 V (5 V tolerant), except where otherwise noted.
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I/O Connector (JP2)
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Table 1. EZ80190 Module Peripheral Bus Connector Pin Identification* (Continued) Pull Up/Down*
Pin # 23 24 25 26 27 28 29 30 31 32 33 34 35 36
Symbol A18 A16 A19 GND A2 A1 A11 A12 A4 A20 A5 A17 Reserved DIS_Flash
Signal Direction Comments Bidirectional Bidirectional Bidirectional VSS/Ground (0 V). Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional
PU 10 K
Input
A Low disables onboard Flash memory. Flash is enabled if DIS_Flash is not connected; CMOS Input 3.3 V (5 V tolerant).
37 38 39 40 41 42 43 44 45
A21 VCC A22 A23 CS0 CS1 CS2 D0 D1 PU 4k7 PU 4k7
Bidirectional 3.3 V supply input pin. Bidirectional Bidirectional Output Output Output Bidirectional Bidirectional
Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0-D7 and A0-A23 should be below 10 pF to satisfy timing requirements for the CPU. All unused inputs should be pulled to either VDD or GND, depending on their inactive levels, to reduce power consumption and to reduce noise sensitivity. To prevent EMI, the EZ80CLK output can be deactivated via software in the EZ80190 Peripheral Power-Down Register. All inputs are CMOS level 3.3 V (5 V tolerant), except where otherwise noted.
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I/O Connector (JP2)
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Table 1. EZ80190 Module Peripheral Bus Connector Pin Identification* (Continued) Pull Up/Down* PU 4k7 PU 4k7 PU 4k7 PU 4k7
Pin # 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
Symbol D2 D3 D4 D5 GND D7 D6 MREQ IORQ GND RD WR INSTRD BUSACK BUSREQ
Signal Direction Comments Bidirectional Bidirectional Bidirectional Bidirectional VSS/Ground (0 V).
PU 4k7
Bidirectional Bidirectional Bidirectional Bidirectional VSS/Ground (0 V). Bidirectional Bidirectional Output Output
PU 2k2
Input
Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0-D7 and A0-A23 should be below 10 pF to satisfy timing requirements for the CPU. All unused inputs should be pulled to either VDD or GND, depending on their inactive levels, to reduce power consumption and to reduce noise sensitivity. To prevent EMI, the EZ80CLK output can be deactivated via software in the EZ80190 Peripheral Power-Down Register. All inputs are CMOS level 3.3 V (5 V tolerant), except where otherwise noted.
Peripheral Bus Connector (JP1)
Figure 3 illustrates the pin layout of the 60-pin I/O Connector (JP2) of the EZ80190 Module. The eZ80(R) Development Platform, however, features a 50-pin connector. The EZ80190 Module is designed to interface pin 60 of its JP2 connector to pin 50 of the eZ80(R) Development Platform's JP2 connector so that pins 1-10 of the EZ80190 Module overlap the edge of the eZ80(R) Development Platform. Table 2 identifies the pins and their functions.
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Peripheral Bus Connector (JP1)
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Figure 3. EZ80190 Module I/O Connector Pin Configuration--JP2 Table 2. EZ80190 Module I/O Connector Pin Identification* Pull Up/Down Signal Direction Bidirectional Bidirectional Bidirectional
Pin # 1 2 3
Symbol PA7 PA6 PA5
Comments
Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0-D7 and A0-A23 should be below 10 pF to satisfy timing requirements for the CPU. All unused inputs should be pulled to either VDD or GND, depending on their inactive levels, to reduce power consumption and to reduce noise sensitivity. To prevent EMI, the EZ80CLK output can be deactivated via software in the EZ80190 Peripheral Power-Down Register. All inputs are CMOS level 3.3 V (5 V tolerant), except where otherwise noted.
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Peripheral Bus Connector (JP1)
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Table 2. EZ80190 Module I/O Connector Pin Identification* (Continued) Pull Up/Down Signal Direction Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional 3.3 V supply input pin. VSS/Ground (0 V). Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional VSS/Ground (0 V). Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional
Pin # 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
Symbol PA4 PA3 PA2 PA1 PA0 VCC GND PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 GND PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
Comments
Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0-D7 and A0-A23 should be below 10 pF to satisfy timing requirements for the CPU. All unused inputs should be pulled to either VDD or GND, depending on their inactive levels, to reduce power consumption and to reduce noise sensitivity. To prevent EMI, the EZ80CLK output can be deactivated via software in the EZ80190 Peripheral Power-Down Register. All inputs are CMOS level 3.3 V (5 V tolerant), except where otherwise noted.
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Peripheral Bus Connector (JP1)
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Table 2. EZ80190 Module I/O Connector Pin Identification* (Continued) Pull Up/Down Signal Direction Bidirectional Bidirectional VSS/Ground (0 V). Bidirectional PD 4k7 Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Output Input ZDI Data Output pin; not used with the EZ80190 Module. ZDI Data Input pin. VSS/Ground (0 V). Output PU 10 K PU 10 K Input Input Active High trigger event indicator; not used with the EZ80190 Module. ZDI Clock. High on reset enables ZDI mode; Low on reset enables OCI debug. JTAG Test Mode Select Input; not used with the EZ80190 Module. RTC supply from GoldCap (or external battery). Output PU 4k7 Bidirectional Synchronous CPU clock output. I2C Bus Clock. VSS/Ground (0 V). PU 4k7 Bidirectional Power I2C Data Clock. VSS/Ground (0 V).
Pin # 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
Symbol PD7 PD6 GND PD5 PD4 PD3 PD2 PD1 PD0 TDO TDI GND TRIGOUT TCK TMS RTC_VDD EZ80CLK I2CSCL GND I2CSDA GND
Comments
Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0-D7 and A0-A23 should be below 10 pF to satisfy timing requirements for the CPU. All unused inputs should be pulled to either VDD or GND, depending on their inactive levels, to reduce power consumption and to reduce noise sensitivity. To prevent EMI, the EZ80CLK output can be deactivated via software in the EZ80190 Peripheral Power-Down Register. All inputs are CMOS level 3.3 V (5 V tolerant), except where otherwise noted.
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Peripheral Bus Connector (JP1)
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Table 2. EZ80190 Module I/O Connector Pin Identification* (Continued) Pull Up/Down PU 10 K Signal Direction Input
Pin # 49
Symbol FlashWE
Comments A Low enables a Write to external Flash memory boot block area. If this pin is unconnected, the Flash memory boot block area is write-protected. VSS/Ground (0 V).
50 51 52
GND CS3 DIS_IRDA PU 10 K Output Input
Connected to the CS8900 EMAC. A Low disables the onboard IRDA transceiver to use PC0/PC1 UART pins externally; not used with the EZ80190 Module. Reset Output from module or push-button reset. Driving the WAIT pin Low forces the CPU to provide additional clock cycles for an external peripheral or external memory to complete its Read or Write operation; not used with the EZ80190 Module. 3.3 V supply input pin. VSS/Ground (0 V).
53 54
RESET WAIT
PU 2k2 PU 2k2
Bidirectional Input
55 56 57
VCC GND HALT_SLP
Output, Active A Low on this pin indicates that the CPU enters Low either HALT or SLEEP mode because of execution of either a HALT or SLP instruction. PU 10 K Schmitt Trigger Input, Active Low The NMI input is a higher priority input than the maskable interrupts. It is always recognized at the end of an instruction, regardless of the state of the interrupt enable control bits. This input includes a Schmitt trigger to allow RC rise times. This external NMI signal is combined with an internal NMI signal generated from the WDT block before being connected to the NMI input of the CPU. 3.3 V supply input pin. NC Reserved--No Connection.
58
NMI
59 60
VCC Reserved
Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0-D7 and A0-A23 should be below 10 pF to satisfy timing requirements for the CPU. All unused inputs should be pulled to either VDD or GND, depending on their inactive levels, to reduce power consumption and to reduce noise sensitivity. To prevent EMI, the EZ80CLK output can be deactivated via software in the EZ80190 Peripheral Power-Down Register. All inputs are CMOS level 3.3 V (5 V tolerant), except where otherwise noted.
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Peripheral Bus Connector (JP1)
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Onboard Component Description
Logic-Level I/Os
The I/O connector features 32 general-purpose 3.3 V CMOS I/O pins that can be used as outputs or inputs interfacing to external logic. All I/Os are 5 V tolerant. Some of the General-Purpose I/O pins support dual mode functions (SPI, I2C, UARTs, and bit I/O with edge- or level-triggered interrupt functions on each pin). For more information on EZ80190 dual modes, please refer to the EZ80190 Product Specification (PS0066).
Onboard Battery Backup
An onboard 0.1 F capacitor (GoldCap) is used to bridge power outages of 2-4 hours if the power supply to the module is disconnected. The capacitor is charged to 3.1 V during normal operation and is discharged through the on-chip Real Time Clock. The VRTC pin is available on the I/O connector of the module to connect external components to a power supply or to a larger GoldCap. Caution: Do not connect a Lithium Battery to the GoldCap capacitor, because onboard charging circuitry for the capacitor can destroy the lithium battery.
Ethernet Media Access Controller
The EZ80190 contains a CS8900A EMAC which is attached to the data/address bus of the processor. This chip is connected to the processor's CS3 Chip Select, A0-A3, D0-D7, RD, WR, and PD4 pins for interrupt purposes. Connection of pins PD6 and PD7 for LANACT (wake-up from sleep) and SLEEP is optional and resistor-selectable onboard.
Ethernet LEDs
There are two green LEDs, a Link LED and a LAN LED, that are located adjacent to each other on the EZ80190 Module. A steady LAN LED (top) indicates received link pulses from the Ethernet. A flashing Link LED (bottom) indicates Traffic (RX or TX) on the LAN.
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Onboard Component Description
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An RJ45 loopback connector can be used to verify the correct operation of the Receiver and the Transmitter. The green LED should be on if RX+ is connected with TX+ and RX- is connected with TX-.
Ethernet Connector
The EZ80190 is equipped with an RJ45 connector that features integrated magnetics (transformer, common mode chokes). The remaining pins on the onboard RJ45 connector are not connected. Node assignments for the RJ45 Ethernet connector are shown in Table 3.
Table 3. Ethernet Connector Pin Assignments Pin 1 2 3 6 Function TX+ TX- RX+ RX-
Node assignment, in contrast to hub assignment, means that a straight-through cable (equivalent pin numbers on both sides of the cable are connected to each other) is used to attach the board to an Ethernet hub or switch. To connect the EZ80190 Module directly to another node (e.g., a personal computer), a crossover cable must be used. The EMAC can be additionally protected by placing a U9 ESD protection array on the module. This array can be either of the LCDA15C-6 (Semtech) or ESDA25B1 (ST Microelectronics) devices.
GPIO Pins for Enabling LAN Activity, Sleep, Interrupt
GPIO input bit PD4 serves as an active High interrupt input for the EMAC's INTRQ0 output. GPIO output bit PD7 can be used to place the EMAC into SLEEP mode. In SLEEP mode, the CS8900 draws less current, because only the receiver is operating. A zero-Ohm resistor at position R14 on the EZ80190 is required for this function. In this case, the PD6 pin is not available for GPIO on the I/O connector. If LAN activity is detected, the LANACT signal is pulled Low. The LANACT is connected to GPIO input PD6 and can be used in interrupt edge-detection mode to wake up and reinitialize the Ethernet chip. A zero-Ohm resistor at position R15 on
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Ethernet Media Access Controller
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the module is required for this function. In this case, the PD6 pin is not available for GPIO on the I/O connector.
EMAC Ports
The I/O base address is user-selectable. The EMAC is connected as an 8-bit device.
EMAC Access
For 50MHz operation, set CS3_CTL (I/O address 0xB3) to 0xF8 (7 wait states for I/O). CS3 is used for selecting the Ethernet MAC. By pulling JP1 pin 25 (DIS_Eth) Low, access to the Ethernet MAC can be disabled on a per-cycle basis.
Memory
The EZ80190 offers SRAM and Flash memories and the wait states that support memory operations, as described in this section.
Wait States
To ensure that valid data is read from or written to slower memories, a number of wait states must be inserted into the memory or I/O access operations by the processor. The number of wait states that are required should be added by programming the chip select control registers. To calculate the minimum number of wait states required, refer to Table 4.
Table 4. Chip Frequency to Wait State Cycle Time Calculation MHz 20 24 40 50 Cycle Time 50.0 ns 41.7 ns 25.0 ns 20.0 ns
Static RAM
The EZ80190 features 512 KB of fast SRAM. Access speed is typically 12 ns or faster, allowing zero-wait-state operation at 50 MHz. With the CPU at 50 MHz,
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Memory
EZ801905050MOD EZ80190 Module Product Specification
15
onboard SRAM can be accessed with zero wait states. The CS1_CTL register can be set to 08h (no wait states).
Flash Memory
The Flash Boot Loader, application code, and user configuration data are held permanently in NOR Flash memory. A typical application requires eight times more ROM for code than RAM. As an example, for 128 KB onboard SRAM, 1 MB of ROM is required. The EZ80190 allows NOR Flash memories between 4 megabits (512 KB) and 32 megabits (4 MB) to be used. The chips are housed in wide TSOP40 cases. Typical Flash ROM access time is 100 ns. For 50 MHz CPU operation, set the Chip Select Control register CS0_CTL (I/O address 0xAA) to 0xA8. This setting selects 5 wait states. CS0 is used for selecting Flash memory. By pulling JP1 pin 26 (DIS_Flash) Low, access to Flash memory can be disabled on a per-cycle basis.
Real-Time Clock
An onboard real-time-clock operates continually, even if the system power supply is down. An onboard capacitor (GoldCap) or external accumulator/battery serves as a standby power supply. The Real-Time-Clock M41T11 contains Binary Coded Decimal (BCD) counting registers for Seconds, Minutes, Hours, Day, Month, and Year; a Century bit and 56 bytes of backed-up RAM are also included. The fully charged 0.1 F GoldCap bridges power outages with a maximum of 4 hours. The GoldCap, in contrast to a battery or an accumulator, offers the dual advantage of no service (replacement) requirements and no effects upon memory. The I2C addresses of the RTC are 0xD0 for WRITE and 0xD1 for READ. The I2C sequence for writing to the RTC is: Start 0xD0 RegNo VALUE1 ... VALUEn Stop and the sequence for reading from the RTC is: Start 0xD1 RegNo VALUE1 ... VALUEn Stop where VALUE1...VALUEn... are sent by the RTC. The processor (I2C Master) requests another value by sending an ACK. The first register to be read is set by a preceding WRITE sequence, without sending data values. Clock updates do not occur while any of the seven clock registers are being read. See Figure 5.
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Real-Time Clock
EZ801905050MOD EZ80190 Module Product Specification
16
Table 5. Real-Time Clock Registers Data Address 0 1 2 3 4 5 6 7 OUT D7 ST X CEB* X X X CB X X X D6 D5 10 Seconds 10 Minutes 10 Hours X X X D4 D3 D2 D1 D0 Function/Range BCD Format Seconds Minutes Hours Day Date Month Year Control 00-59 00-59 0-1/00-23 01-07 01-31 01-12 00-99
Seconds Minutes Hours Day Date Month Years Calibration
10 Date X 10 M.
10 Years FT S
Notes: *When CEB is set to 1, CB toggles from 0 to 1 or from 1 to 0 every 100 years, depending upon the initial vale set. When CEB is set to 0, CB does not toggle. Keys: S = Sign bit, FT = Frequency Test bit, ST = Stop bit, OUT = Output level, X = Don't care, CEB = Century Enable bit, CB = Century Bit.
For further details, please refer to the M41T11 data sheet from SGS-Thomson at www.st.com.
Reset Generator
The onboard Reset Generator Chip performs reliable Power-On Reset. The chip generates a reset pulse with a duration of 200 ms if the power supply drops below 2.93 V. This reset pulse ensures that the board always starts in a defined condition. The RESET pin on the I/O connector reflects the status of the RESET line. It is a bidirectional pin for resetting external peripheral components or for resetting the EZ80190 with a low-impedance output (e.g. a 100-Ohm pushbutton).
Serial Interface Ports
The processor contains two 16550-style UARTs with programmable baud rate generators. When the EZ80190 Module is plugged in to the eZ80(R) Development Platform, UART0 is connected to a console connector and UART1 is connected to a modem connector. There are no RS232-level shifters on the EZ80190. Note: Do not connect an RS-232 interface without level shifters.
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Reset Generator
EZ801905050MOD EZ80190 Module Product Specification
17
Physical Dimensions
The footprint of the EZ80190 Module PCB is 63.5 mm x 78.7 mm. With an RJ-45 Ethernet connector, the overall height is 25 mm. See Figure 4.
63.5 mm
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78.7 mm
Figure 4. Physical Dimensions of the EZ80190 Module
PRELIMINARY
63.5 mm
Serial Interface Ports
EZ801905050MOD EZ80190 Module Product Specification
18
Figure 5 illustrates the top layer silkscreen of the EZ80190 Module.
Figure 5. EZ80190 Module--Top Layer
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19
Figure 6 illustrates the bottom layer silkscreen of the EZ80190 Module.
Figure 6. EZ80190 Module--Bottom Layer
ESD/EMI Protection
Caution: The EZ80190 is a component that is intended to be part of a system design for end-user devices. Therefore, the user must exercise caution to use ESD protection on the I/O pins. The EMAC can be additionally protected by placing an ESD protection array on the EZ80190 at position U9. Either use ESDA25B1 from ST Microelectronics or LCDA15C-6 from Semtech. A mounting hole on the board can be used for grounding the shield of the Ethernet RJ45 jack to prevent surge or ESD currents from flowing through the digital circuitry. The RJ45 Ethernet Connector on the EZ80190 contains a transformer and common mode chokes for EMI suppression. Caution: CMOS I/Os are ESD-sensitive and must be handled with care. Handling of the module should be performed in ESD-safe environments (for example with a wrist-wrap attached). When
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ESD/EMI Protection
EZ801905050MOD EZ80190 Module Product Specification
20
developing applications, the user must provide for proper ESD protection on external, user-accessible I/Os (e.g. suppressor arrays for the I/Os). The components are mounted on a multilayer PCB to provide a stable ground plane for onboard components. The module features several GND pins next to pins with higher switching frequency for short ground returns. If unused, the clock output can be separated from the module header by removing a series resistor on the module. Removing the series resistor further reduces electromagnetic emissions.
Absolute Maximum Ratings
Stresses greater than those listed in Table 6 can cause permanent damage to the device. These ratings are stress ratings only. Operation of the device at any condition outside those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. For improved reliability, unused inputs should be tied to one of the supply voltages (VDD or VSS).
Table 6. Absolute Maximum Ratings Parameter Standard operating temperature Storage temperature Operating Humidity (RH @ 50C) Operating Voltage (5%) Min 0 -45 25% -- Max +70 +85 90% 3.3 V Units C C
Power Supply
The eZ80TM Webserver-i E-NET Module requires a regulated external 3.3 VDC/ 0.5A power supply. You may use a Low Dropout Regulator (LDO) to get 3.3 V from 5 V or use the following switcher circuit to generate 3.3 V from unregulated 10-28V power supply. Power connections follow these conventional descriptions:
Connection Power Ground Circuit VCC GND Device VDD VSS
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Power Supply
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21
Switcher 10-28V 3.3V
U1 LM2575S-ADJ 10-28V V IN C1 1000uF C2 100n 1 VIN G N D 3 FB OVOUT N / O F F 5 4 2 L1
To Module
VDD 3.3V
R1 5k6 1% C3 470uF/6.3V Low ESR 330uH/1A
D1 1A/30V R2 3k3 1%
GND
GND
LDO 5V 3.3V
4-6V VCC U1 LM3940 VI G N D VO
VDD 3.3V
C3 Low ESR 470uF/6.3V GND
C1 100n GND
Figure 7. Power Supply Examples
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Power Supply
EZ801905050MOD EZ80190 Module Product Specification
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Document Number Description
The Document Control Number that appears in the footer of each page of this document contains unique identifying attributes, as indicated in the following table:
PS 0191 01 1003 Product Specification Unique Document Number Revision Number Month and Year Published
Change Log
Rev 01 Date October 2003 Purpose Original issue By M. Staubermann
PS019101-1003
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Document Number Description
EZ801905050MOD EZ80190 Module Product Specification
Schematic Diagrams
Figures 8 through 15 present the schematics of the EZ80190 Module.
X1 R13 ETHIRQ -SLEEP -ACTIVE ETHIRQ -SLEEP -ACTIVE 0R R14 0603 0R R15 0603
23
=
PD4 PD7
PA[0..7]
XIN
3
OUT
OE
1 4k7 0603
-BUSREQ
PD6 CLK_OUT
PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 -BUSACK
PD[0..7] PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
50.000MHz, 3.3V SG-710 PA[0..7] PA[0..7]
don't stuff
PHI BUSREQ VSS VDD PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 BUSACK EXTAL XTAL VSS VDD PD7/RI0 PD6/DCD0 PD5/DSR0 PD4/DTR0 PD3/SS0/CTS0 PD2/SCK0/RTS0 PD1/SDA0/MOSI0/RxD0 PD0/SCL0/MISO0/TxD0
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
PC[0..7] 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 ZDA ZCL -RESET -IOREQ -INSTRD -HALT
-WR -RD -CS[0..3]
-WR -RD -CS[0..3]
-CS0 --> FLASH -CS1 --> RAM -CS2 --> ext. IO -CS3 --> ETH
D[0..7] A[0..23] D[0..7] A[0..23]
-MREQ -WR -RD -CS0 -CS1 -CS2 -CS3 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13
-BUSREQ -BUSACK -MREQ CLK_OUT
-BUSREQ -BUSACK -MREQ CLK_OUT
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
MREQ WR RD CS0 CS1 CS2 CS3 VDD VSS A0 A1 A2 A3 A4 A5 A6 A7 VDD VSS A8 A9 A10 A11 A12 A13
U1
EZ80190
TQFP100
TEST PC7/RI1 PC6/DCD1 PC5/DSR1 PC4/DTR1 PC3/SS1/CTS1 PC2/SCK1/RTS1 PC1/SDA1/MOSI1/RxD1 PC0/SCL1/MISO1/TxD1 VSS VDD PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 ZDA ZCL RESET IORQ INSTRD HALT
PB[0..7] PC[0..7] PD[0..7]
PB[0..7] PC[0..7] PD[0..7]
ZDA ZCL
ZDA ZCL
PB[0..7]
-RESET -IOREQ R4 -INSTRD -HALT 1k 0603 -NMI
-RESET -IOREQ -INSTRD -HALT -NMI
PC1
PC0
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 -NMI A14 A15 R31 0R 0603 PA7 0R R32 0603 0R R33 0603 PA6 C18 1nF 0603 C19 1nF 0603 C20 1nF 0603 A16 A17 A18 A19 A20 A21 A22 A23 D0 D1 D2 D3 D4 D5 D6 D7 A[0..23] D[0..7]
don't stuff
IICSDA IICSCL
R30 0R 0603
IICSDA IICSCL
Figure 8. EZ80190 Module Schematic Diagram, #1 of 9--CPU
PS019101-1003 PRELIMINARY Schematic Diagrams
A14 A15 VDD VSS A16 A17 A18 A19 A20 A21 A22 A23 VDD VSS D0 D1 D2 D3 D4 D5 D6 D7 VDD VSS NMI
place caps close to pins 97, 8, 38, 48
EZ801905050MOD EZ80190 Module Product Specification
24
U2 D[0..7] A[0..23] D[0..7] A[0..23] A18 A0 A1 A2 A3 -CSRAM D0 D1 D2 D3 -WR A12 A9 A6 A4 A17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 A0 A1 A2 A3 A4 CE I/O0 I/O1 VDD VSS I/O2 I/O3 WE A5 A6 A7 A8 A9 N.C. A18 A17 A16 A15 OE I/O7 I/O6 VSS VDD I/O5 I/O4 A14 A13 A12 A11 A10 N.C. 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 A20 A16 A15 A14 A13 -RD D7 D6 D5 D4 A11 A8 A10 A7 A5 A19 D7 D6 D5 D4 D3 D2 D1 D0 10 9 8 7 6 5 4 3 2 RN1
A21/ A22/ A23 not us ed her e
-CSRAM
-CS1 -RD -WR
-CS1 -RD -WR
=
1 9 x 4k7 SIP10
512kx8 fast SRAM SOJ36.400 AS7C34096-10JC V3.3
VDD C1 100nF 0603 VSS
GND
Figure 9. EZ80190 Module Schematic Diagram, #2 of 9--36-Pin SRAM Device
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Schematic Diagrams
EZ801905050MOD EZ80190 Module Product Specification
25
D[0..7]
U3 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 21 20 19 18 17 16 15 14 8 7 36 6 5 4 3 2 1 40 13 37 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19
30 31
A[0..23]
I nt el - Ty pe
U4 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CE OE WE RP WP VPP 25 26 27 28 32 33 34 35 22 24 9 10 12 11 29 38 DFLASH0 DFLASH1 DFLASH2 DFLASH3 DFLASH4 DFLASH5 DFLASH6 DFLASH7 -CSFLASH -RD -WR -RESFLASH -WP VPP A21 A20 R5 0R 0603 2 5 6 9 10 15 16 19 20 23 1B1 1B2 1B3 1B4 1B5 2B1 2B2 2B3 2B4 2B5 1A1 1A2 1A3 1A4 1A5 2A1 2A2 2A3 2A4 2A5 1OE 2OE 74CBTLV3384 SO24.300 3 4 7 8 11 14 17 18 21 22 1 13 D0 D1 D2 D3 D4 D5 D6 D7
C2 100nF 0603
VDD VDD
-CSFLASH
Pi n37=N. C. f or 4M t bi Fl as hes
D[0..7] A[0..23] -RD -WR -CS0 -DIS_FLASH D[0..7] A[0..23] -RD
VSS VSS
N.C. N.C.
A20/ A21 us ed f or 16/ 32M t - Fl as h bi
Flash 1Mx8 3.3V TSOP40.20MM MT28F008B3VG
A22/ A23 not us ed her e
-DIS_FLASH 1
23 39
U6A 2
U5A -CS0 -FLASH_EN 1 3 2 74LCX32 TSSOP14 -CSFLASH
-WR -CS0 -DIS_FLASH VDD -RESET R7 10k 0603 -FLASHWE 3 VSS U6B GND 4 -WP R6 10k 0603 74LCX04 TSSOP14 V3.3
-RESET -FLASHWE
= -RESFLASH
-FLASHWE
Note: Must be pulled Low externally for programming.
74LCX04 TSSOP14
Figure 10. EZ80190 Module Schematic Diagram, #3 of 9--NOR Flash Device
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Schematic Diagrams
EZ801905050MOD EZ80190 Module Product Specification
26
R8 10k 0603
Dual-LED assembly, right angle, grn/grn
LD1 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 -LANLED -LINKLED Y1 20.000 MHz HC49 R12 RXDRXD+ TXDTXD+ 4k99/1% 0603 -LANLED
25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
SD10 SD11 DVSS DVDD SD12 SD13 SD14 SD15 CSOUT DMACK0 DMARQ0 DMACK1 DMARQ1 DMACK2 DMARQ2 DVSS DVDD DVSS CHIPSEL EEDATAIN EEDATAOUT (TDO) EESK EECS ELCS AVSS
R11 4k7 0603 ETHIRQ
SA0 SA1 SA2 SA3 SA[0..3]
SA13 SA14 SA15 SA16 DVSS DVDD DVSS SA17 SA18 SA19 IOR IOW AEN (TCK) IOCHRDY SD0 SD1 SD2 SD3 DVDD DVSS SD4 SD5 SD6 SD7 RESET
-DIS_ETH
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
green green
R9 100 0603
R10 100 0603
SD9 SD8 MEMW MEMR INTRQ2 INTRQ1 INTRQ0 IOCS16 MEMCS16 INTRQ3 SHBE SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 REFRESH SA12
U7 CS8900A-CQ3
TQFP100
LANLED LINKLED/HC0 XTAL2 XTAL1 AVSS AVDD AVSS RES RXDRXD+ AVDD AVSS TXDTXD+ AVSS AVDD DODO+ CICI+ DIDI+ BSTATU S/HC1 SLEEP TEST
upper LED
-LINKLED
lower LED
5682F5;5 LED5682F
ESD protection array
U8 RD+ 1 RD2 3 4 8 TD+ 7 TD6 5 LCDA15C-6 SO8.150 CASE 9 J1 GND
-SLEEP
i nt . Pul l - Up
GND TXDR1 8R2 0603 TDC3 560pF 0603 TD+ 8R2 0603 R3 100 0603 CTD RD-
device addresses: 00300h bis 0030Fh
-ETHRD -ETHWR -DIS_ETH -ETHRD -ETHWR -DIS_ETH
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
TXD+ -ETHRD -ETHWR C4 100nF 0603 R2 RXD-
1 2 3 4 CRD 5 6 8
SD0 SD1 SD2 SD3
SD4 SD5 SD6 SD7
RXD+
RD+ C5 100nF 0603
SD[0..7] SA[0..3] ETHIRQ -SLEEP -ACTIVE
SD[0..7] SA[0..3]
SD[0..7]
V3.3 ETHIRQ VDD -SLEEP -ACTIVE VSS
through-hole solder pad place near FAST JACK
L1 ferrite 1210
JP4 HEADER 1 SIP1
C6 100nF 0603
10
s hi el d
HFJ11-1041(E) HALOFASTJACK
do not stuff
CASE
=
-LANLED GND
do not stuff
Figure 11. EZ80190 Module Schematic Diagram, #4 of 9--Ethernet Module
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1
plane or big trace
CASE
TX+ TXRX+ RX-
<- > <- > <- > <- >
1 2 3 6
Schematic Diagrams
EZ801905050MOD EZ80190 Module Product Specification
27
U9 D[0..7] A[0..23] D[0..7] A[0..23] D0 D1 D2 D3 D4 D5 D6 D7 D[0..7] -ETHWR -WR -CSETH -RD -CS3 -CS3 3 4 5 6 7 8 9 10 13 14 11 2 1 23 A0 A1 A2 A3 A4 A5 A6 A7 OEAB LEAB CEAB OEBA LEBA CEBA 74LCX543 TSSOP24 CLK_OUT CLK_OUT U10 A0 A1 A2 A3 A[0..23] CSETH_P 2 3 4 5 6 7 8 9 11 1 D1 D2 D3 D4 D5 D6 D7 D8 LE OE 74LCX573 TSSOP20 U5B -RD U6C 5 6 CSETH_P -CSETH1D 4 6 5 74LCX32 TSSOP14 -ETHRD Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 19 18 17 16 15 14 13 12 SA0 SA1 SA2 SA3 SA[0..3] -ETHWR -ETHRD -ETHRD -ETHWR B0 B1 B2 B3 B4 B5 B6 B7 22 21 20 19 18 17 16 15 SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 SD[0..7] SD[0..7] SA[0..3] SD[0..7] SA[0..3]
-RD -WR
-RD -WR
=
-CSETH -CSETH
74LCX04 TSSOP14 -CSETH CLK_OUT 2 3 D
don't stuff
10 4 U11A Q 5 -CSETH1D CLK_OUT CL Q 6 74LCX74 TSSOP14 V3.3 12 11 D CLK CL Q 8 74LCX74 TSSOP14 V3.3 U11B Q 9 R17 0R 0603 PR PR
R16 0R 0603
U5C -WR 9 8 -CSETH2D 10 74LCX32 TSSOP14 V3.3 -ETHWR
CLK
13
1
VDD VSS
GND
Figure 12. EZ80190 Module Schematic Diagram, #5 of 9--Ethernet Module Logic
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Schematic Diagrams
EZ801905050MOD EZ80190 Module Product Specification
28
power supervisor
V3.3 C7 100nF 0603
3
U12
VDD
R 18 2k2 0603 RESET RESET RESET
RESET GND
2
open-drain
C8 10nF 0603
M AX6328UR29 SO T- L3 23-
alternative: Maxim MAX6802UR29D3
real-time clock
Gold Cap C9 0,1F GOLDCAP_SD_V
1
R19 V3. 3 D1 TM M BAT 41 M I I ELF_AK NM R20 100 0603 RTC _VDD RTC _VDD
C 10 100nF 0603 VBAT 8 3 U 13 1 2 Y2 32.7 68kHz XTAL3
RTC _VDD 0R 0603
V+ GND VBAT
O SC I OS CO
SD A SCL
5 6 7 R 23
IC SD A I IIS CL C
FT/OUT
R21 4k7 0603
R 22 4k7 0603 IC SD A I IIS CL C IC SD A I IIS CL C VD D VSS
M 41T11M 6 SO 8. 150
C11 unplce a 0603
I2C bus address:
{D0} H /{D1} H
GND
Figure 13. EZ80190 Module Schematic Diagram, #6 of 9--Ethernet Module Peripherals
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4
4k7 0603
V3.3
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Schematic Diagrams
EZ801905050MOD EZ80190 Module Product Specification
29
A[0..23] D[0..7] -CS[0..3]
A[0..23] D[0..7]
connector 1
JP1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 PA7 PA5 PA3 PA1 V3.3_EXT PB7 PB5 PB3 PB1 GND_EXT PC6 PC4 PC2 PC0 PD6 PD5 PD3 PD1 GND_EXT ZCL RTC_VDD IICSCL IICSDA -FLASHWE -CS3 -RESET V3.3_EXT -HALT V3.3_EXT
connector 2
JP2 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 PA6 PA4 PA2 PA0 GND_EXT PB6 PB4 PB2 PB0 PC7 PC5 PC3 PC1 PD7 GND_EXT PD4 PD2 PD0 ZDA EZ80CLK GND_EXT GND_EXT GND_EXT NOTUSED1 GND_EXT -NMI NC
-CS[0..3] GND_EXT A6 A10 GND_EXT A8 A13 A15 A18 A19 A2 A11 A4 A5 -DIS_ETH A21 A22 -CS0 -CS2 D1 D3 D5 D7 -MREQ GND_EXT -WR -BUSACK
IICSDA IICSCL CLK_OUT -DIS_FLASH -FLASHWE RTC_VDD PB[0..7] PC[0..7] PD[0..7] PA[0..7] -DIS_ETH -RESET -RD -WR -IOREQ -MREQ -INSTRD -HALT -BUSREQ -BUSACK -NMI ZDA ZCL
IICSDA IICSCL CLK_OUT -DIS_FLASH -FLASHWE RTC_VDD PB[0..7] PC[0..7] PD[0..7] PA[0..7] -DIS_ETH -RESET -RD -WR -IOREQ -MREQ -INSTRD -HALT -BUSREQ -BUSACK -NMI ZDA ZCL V3.3 R27 10k 0603 R28 10k 0603 R26 2k2 0603 R25 10k 0603 R24 33 0603 EZ80CLK
place near eZ80 output (PHI)
V3.3_EXT A0 A3 V3.3_EXT A7 A9 A14 A16 GND_EXT A1 A12 A20 A17 -DIS_FLASH V3.3_EXT A23 -CS1 D0 D2 D4 GND_EXT D6 -IOREQ -RD -INSTRD -BUSREQ
Header 30x2
Header 30x2
peripheral bus connector
I/O connector
Pin 50 open, to be keyed
R29 10k 0603 NOTUSED1
(* W T *) AI
V3.3_EXT GND_EXT
GND
Figure 14. EZ80190 Module Schematic Diagram, #7 of 9--Headers
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Schematic Diagrams
EZ801905050MOD EZ80190 Module Product Specification
30
common power plane
V3.3 VDD C12 22uF SMT7343 GND C13 22uF SMT7343
no power supply on board Input: VDD ( = V3.3) = 3.3V 5% Power: Pmax = tbd Ptyp = tbd Current: lmax = tbd ltyp = tbd
C14 1nF 0603
C15 100nF 0603
C16 1nF 0603
C17 100nF 0603 VSS
common ground plane
PCB1
EZ80190 ethernet module board 98Cxxxx-xxx 9
U6D 12 8 13 74LCX04 TSSOP14
U5D 11 74LCX32 TSSOP14
U6E 11 10
unused gates
74LCX04 TSSOP14
U6F 13 12
74LCX04 TSSOP14
Figure 15. EZ80190 Module Schematic Diagram, #8 of 9--Power Supply
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Schematic Diagrams
EZ801905050MOD EZ80190 Module Product Specification
31
Customer Feedback Form
The EZ80190 Module Product Specification If you experience any problems while operating this product, or if you note any inaccuracies while reading this Product Specification, please copy and complete this form, then mail or fax it to ZiLOG (see Return Information, below). We also welcome your suggestions! Customer Information
Name Company Address City/State/Zip Country Phone Fax Email
Product Information
Serial # or Board Fab #/Rev. # Software Version Document Number Host Computer Description/Type
Return Information ZiLOG System Test/Customer Support 532 Race Street San Jose, CA 95126 Phone: (408) 558-8500 Fax: (408) 558-8536 ZiLOG Customer Support Problem Description or Suggestion Provide a complete description of the problem or your suggestion. If you are reporting a specific problem, include all steps leading up to the occurrence of the problem. Attach additional pages as necessary.
_____________________________________________________________________________________________ _____________________________________________________________________________________________ _____________________________________________________________________________________________ _____________________________________________________________________________________________ _____________________________________________________________________________________________
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Customer Feedback Form

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